features ? hvcmos ? technology for high performance ? very low quiescent power dissipation (10a max.) ? output on-resistance (22 typ.) ? integrated bleed resistors on the outputs ? low parasitic capacitances ? dc to 50mhz small signal frequency response ? -60db typical output off isolation at 5.0mhz ? cmos logic circuitry for low power ? excellent noise immunity ? on-chip shift register, latch and clear logic circuitry ? flexible high voltage s upplies applications ? medica l ultrasound imaging ? piezoe lectric transducer drivers block diagram low charge injection 8-channel high voltage analog switches with bleed resistors general description the supertex hv23 2 is a low charge injection 8-channel, high-voltage, analog switch integrated circuit (ic) with bleed resistors. this device can be used in applications requiring high voltage switching controlled by low voltage control signals, such as ultrasound imaging and printers. the bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric transducers. input data is shifted into an 8-bit shift register which can then be retained in an 8-bit latch. to reduce any possible clock feed-through noise, latch enable (le) should be left high until all bits are clocked in. using hvcmos ? technology, this switch combines high voltage bilateral dmos switches and low power cmos logic to provide effcient control of high voltage analog signals. this ic is suitable for various combinations of high voltage supplies, e.g., v pp /v nn : +50v/C150v, or +100v/C100v. le cl sw0 sw1 sw2 sw3 sw4 sw5 sw6 sw7 vpp vnn vdd rgnd dout din clk 8-bit shift register latches level shifters output switches d le cl d le cl d le cl d le cl d le cl d le cl d le cl d le cl supertex inc. supertex inc. www .supertex.com doc.# dsfp-hv232 c071613 hv232
2 absolute maximum ratings parameter value v dd logic power supply voltage -0.5v to +15v v pp - v nn supply voltage 220v v pp positive high voltage supply -0.5v to v nn +200v v nn negative high voltage supply +0.5v to -200v logic input voltages -0.5v to v dd +0.3v analog signal range v nn to v pp peak analog signal current/channel 3.0a storage temperature -65 o c to +150 o c power dissipation: 48-lead lqfp 28-lead plcc 1.0w 1.2w operating conditions sym parameter value v dd logic power supply voltage 1,3 4.5v to 13.2v v pp positive high voltage supply 1,3 40v to v nn +200v v nn negative high voltage supply 1,3 -40v to -160v v ih high level input voltage v dd -1.5v to v dd v il low-level input voltage 0v to 1.5v v sig analog signal voltage peak-to-peak 2 v nn +10v to v pp -10v t a operating free air temperature 0 o c to 70 o c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. notes: 1. power up/down sequence is arbtrary except gnd must be powered -up first and powered down last. 2. v sig must be v nn v sig v pp or floating during power up/down transition. 3. rise and fall times of power supplies v dd , v pp , and v nn should not be less than 1.0msec. pin configuration product marking 48-lead lqfp (top view) 48-lead lqfp 28-lead plcc (top view) 28-lead plcc yy = year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = ?green? packaging *may be part of top marking top marking bottom marking yyww hv232fg lllllllll cccccccc aaa yy = year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = ?green? packaging *may be part of top marking top marking bottom marking yyww hv232pj llllllllll ccccccccccc aaa 1 48 1 28 4 26 package may or may not include the following marks: si or package may or may not include the following marks: si or ordering information part number package option packing hv232fg-g 48-lead lqfp 250/tray hv232fg-g m931 48-lead lqfp 1000/reel hv232pj-g 28-lead plcc 38/tube hv232pj-g m904 28-lead plcc 500/reel typical thermal resistance package ja 48-lead lqfp 52 o c/w 28-lead plcc 48 o c/w -g denotes a lead (pb)-free / rohs compliant package supertex inc. www .supertex.com doc.# dsfp-hv232 c071613 hv232
3 sym parameter 0 o c +25 o c +70 o c unit conditions min max min typ max min max r ons small signal switch on-resistance - 30 - 26 38 - 48 i sig = 5.0ma v pp = +40v v nn = -160v - 25 - 22 27 - 32 i sig = 200ma - 25 - 22 27 - 30 i sig = 5.0ma v pp = +100v v nn = -100v - 18 - 18 24 - 27 i sig = 200ma - 23 - 20 25 - 30 i sig = 5.0ma v pp = +160v v nn = -40v - 22 - 16 25 - 27 i sig = 200ma r ons small signal switch on-resistance matching - 20 - 5.0 20 - 20 % i sig = 5.0ma, v pp = +100v, v nn = -100v r onl large signal switch on-resistance - - - 15 - - - v sig = v pp -10v, i sig = 1.0a r int output switch shunt resistance - - 20 35 50 - - k output switch to r gnd i rint = 0.5ma i sol switch off leakage per switch - 5.0 - 1.0 10 - 15 a v sig = v pp -10v v os dc offset switch off - 300 - 100 300 - 300 mv no load dc offset switch on - 500 - 100 500 - 500 mv no load i ppq quiescent v pp supply current - - - 10 50 - - a all switches off i nnq quiescent v nn supply current - - - -10 -50 - - a all switches off i ppq quiescent v pp supply current - - - 10 50 - - a all switches on, i sw = 5.0ma i nnq quiescent v nn supply current - - - -10 -50 - - a all switches on, i sw = 5.0ma i sw switch output peak current - 3.0 - 3.0 2.0 - 2.0 a v sig duty cycle - 0.1% f sw output switching frequency - - - - 50 - - khz duty cycle = 50% i pp supply current - 6.5 - - 7.0 - 8.0 ma v pp = +40v v nn = -160v all output switches are turning on and off at 50khz with no load - 4.0 - - 5.0 - 5.5 v pp = +100v v nn = -100v - 4.0 - - 5.0 - 5.5 v pp = +160v v nn = -40v i nn supply curent - 6.5 - - 7.0 - 8.0 ma v pp = +40v v nn = -160v all output switches are turning on and off at 50khz with no load - 4.0 - - 5.0 - 5.5 v pp = +100v v nn = -100v - 4.0 - - 5.0 - 5.5 v pp = +160v v nn = -40v i dd logic supply average current - 4.0 - - 4.0 - 4.0 ma f clk = 5.0mhz, v dd = 5.0v i ddq logic supply quiescent current - 10 - - 10 - 10 a --- i sor data out source current 0.45 - 0.45 0.70 - 0.40 - ma v out = v dd -0.7v i sink data out sink current 0.45 - 0.45 0.70 - 0.40 - ma v out = 0.7v c in logic input capacitance - 10 - - 10 - 10 pf --- dc electrical characteristics (over operating conditions unless otherwise specified ) supertex inc. www .supertex.com doc.# dsfp-hv232 c071613 hv232
4 sym parameter 0 o c +25 o c +70 o c unit conditions min max min typ max min max t sd set up time before le rises 150 - 150 - - 150 - ns --- t wle time width of le 150 - 150 - - 150 - ns --- t do clock delay time to data out 55 150 60 - 150 70 150 ns --- t wcl time width of cl 150 - 150 - - 150 - ns --- t su set up time data to clock 15 - 15 8.0 - 20 - ns --- t h hold time data from clock 35 - 35 - - 35 - ns --- f clk clock frequency - 5.0 - - 5.0 - 5.0 mhz 50% duty cycle, f data = f clk /2 t r , t f clock rise and fall times - 1.0 - - 1.0 - 1.0 s --- t on turn on time - 5.0 - - 5.0 - 5.0 s v sig = v pp -10v, r l = 10k t off turn off time - 5.0 - - 5.0 - 5.0 s v sig = v pp -10v, r l = 10k dv/dt maximun v sig slew rate - 20 - - 20 - 20 v/ns v pp = +160v, v nn = -40v - 20 - - 20 - 20 v pp = +100v, v nn = -100v - 20 - - 20 - 20 v pp = +40v, v nn = -160v k o off isolation -30 - -30 -33 - -30 - db f = 5.0mhz, 1.0k/15pf load -58 - -58 - - -58 - f = 5.0mhz, 50 load k cr switch crosstalk -60 - -60 -70 - -60 - db f = 5.0mhz, 50 load i id output switch isolation diode current - 300 - - 300 - 300 ma 300ns pulse width, 2.0% duty cycle c sg(off) off capacitance sw to gnd 5.0 17 5.0 12 17 5.0 17 pf 0v, f = 1.0mhz c sg(on) on capacitance sw to gnd 25 50 25 38 50 25 50 pf 0v, f = 1.0mhz +v spk output voltage spike - - - - 150 - - mv v pp = +40v, v nn = -160v, r l = 50 -v spk - - - - 150 - - +v spk - - - - 150 - - v pp = +100v, v nn = -100v, r l = 50 -v spk - - - - 150 - - +v spk - - - - 150 - - v pp = +160v, v nn = -40v, r l = 50 -v spk - - - - 150 - - ac electrical characteristics (over recommended operating conditions, v dd = 5.0v, unless otherwise specified) supertex inc. www .supertex.com doc.# dsfp-hv232 c071613 hv232
5 data in le clock data out off on v out (typ) 50% 50% 50% 50% t wle t sd t su t h 50% 50% t off 50% t do t on t wcl clr d n+1 d n d n-1 50% 50% 90% 10% logic timing waveforms truth table d0 d1 d2 d3 d4 d5 d6 d7 le clk sw0 sw1 sw2 sw3 sw4 sw5 sw6 sw7 l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on x x x x x x x x h l hold previous state x x x x x x x x x h all switches off notes: 1. the eight switches operate independently. 2. serial data is clocked in on the l to h transition of the clk. 3. the switches go to a state retaining their present condition at the rising edge of le. when le is low the shift register data flow through the latch. 4. d out is high when data in the shift register 7 is high. 5. shift register clocking has no effect on the switch states if le is high. 6. the clr clear input overrides all other inputs. supertex inc. www .supertex.com doc.# dsfp-hv232 c071613 hv232
6 switch off leakage i sol v pp ?10v dc offset on/off v out t on /t off te st circuit 5.0v vpp vnn vdd gnd v pp ?10v r l 10k v out isolation diode current i id v nn v sig crosstalk k cr = 20log v out v in v in = 10 v p ? p @5mhz nc 50 50 charge injection v sig v out 1000pf q = 1000pf x dv out dv out output v oltage spike vout 1k rl 50 +v spk ?v spk off isolation k o = 20log v out v in v in = 10 v p ? p @5mhz r l v out open r gnd r gnd open r gnd r gnd r gnd r gnd rgnd r gnd 5.0v vpp vnn vdd gnd v pp 5.0v v nn vpp vnn vdd gnd 5.0v vpp vnn vdd gnd 5.0v vpp vnn vdd gnd 5.0v vpp vnn vdd gnd 5.0v vpp vnn vdd gnd 5.0v vpp vnn vdd gnd v pp v nn v pp v nn v pp v nn v pp v nn v pp v nn v pp v nn v pp v nn test circuits supertex inc. www .supertex.com doc.# dsfp-hv232 c071613 hv232
7 pin function pin function 1 sw5 25 vnn 2 n/c 26 n/c 3 sw4 27 rgnd 4 n/c 28 gnd 5 sw4 29 vdd 6 n/c 30 n/c 7 n/c 31 n/c 8 sw3 32 n/c 9 n/c 33 din 10 sw3 34 clk 11 n/c 35 le 12 sw2 36 clr 13 n/c 37 dout 14 sw2 38 n/c 15 n/c 39 sw7 16 sw1 40 n/c 17 n/c 41 sw7 18 sw1 42 n/c 19 n/c 43 sw6 20 sw0 44 n/c 21 n/c 45 sw6 22 sw0 46 n/c 23 n/c 47 sw5 24 vpp 48 n/c pin description (28-lead plcc) pin description (48-lead lqfp) pin function pin function 1 sw3 15 n/c 2 sw3 16 din 3 sw2 17 clk 4 sw2 18 le 5 sw1 19 cl 6 sw1 20 dout 7 sw0 21 sw7 8 sw0 22 sw7 9 n/c 23 sw6 10 vpp 24 sw6 11 rgnd 25 sw5 12 vnn 26 sw5 13 gnd 27 sw4 14 vdd 28 sw4 supertex inc. www .supertex.com doc.# dsfp-hv232 c071613 hv232
8 48-lead lqfp package outline (fg) 7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch symbol a a1 a2 b d d1 e e1 e l l1 l2 dimension (mm) min 1.40* 0.05 1.35 0.17 8.80* 6.80* 8.80* 6.80* 0.50 bsc 0.45 1.00 ref 0.25 bsc 0 o nom - - 1.40 0.22 9.00 7.00 9.00 7.00 0.60 3.5 o max 1.60 0.15 1.45 0.27 9.20* 7.20* 9.20* 7.20* 0.75 7 o jedec registration ms-026, variation bbc, issue d, jan. 2001. * this dimension is not specified in the jedec drawing. drawings are not to scale. supertex doc. #: dspd-48lqfpfg version, d041309. 1 seating plane gauge plane l l1 l2 vi ew b view b seating plane top view side view note 1 (index area d1/4 x e1/4) 48 a2 a a1 b d d1 e e1 e note: 1. a pin 1 identifier must be located in the index area indicated. the pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. supertex inc. www .supertex.com doc.# dsfp-hv232 c071613 hv232
9 (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information go to http://www.supertex.com/packaging.html .) 28-lead plcc package outline (pj) .453x.453in. body, .180in. height (max), .050in. pitch symbol a a1 a2 b b1 d d1 e e1 e r dimension (inches) min .165 .090 .062 .013 .026 .485 .450 .485 .450 .050 bsc .025 nom .172 .105 - - - .490 .453 .490 .453 .035 max .180 .120 .083 .021 .032 .495 .456 .495 .456 .045 jedec registration ms-018, variation ab, issue a, june, 1993. drawings not to scale . supertex doc. #: dspd-28plccpj, version b031111. .150max .048/.042 x 45 o .075max d d1 e1 e t op vi ew v iew b a a2 a1 seating plane note 1 (index area) .056/.042 x 45 o base plane .020min b vi ew b b1 horizontal side v iew v ertical side vi ew note 2 .020max (3 places) r e 4 26 28 1 notes: 1. a pin 1 identifier must be located in the index area indicated. the pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. actual shape of this feature may vary. supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. (website: http//www .supertex.com) ?2013 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com hv232 doc.# dsfp-hv232 c071613
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